Amplifying photoelectric conversion devices increase the sensitivity of the photoelectric conversion process by amplifying, within each pixel, the signal generated by each pixel.
FIGS. 45 through 48 are schematic diagrams showing a conventional photoelectric conversion device, as disclosed in Ishida et al., "The Development of 1.6 Million-pixel Amplification Type Image Sensor BCAST," The Journal of the Institute of Image Information and Television Engineers (Japan), Vol. 51, No. 2, pp. 211-218 (1997). FIG. 45 is a plan view; FIG. 46 is a cross-sectional view taken along the X1-X2 line shown in FIG. 45; FIG. 47 is a cross-sectional view taken along the Y1-Y2 line of FIG. 45; and FIG. 48 is a cross-sectional view taken along the Y3-Y4 line of FIG. 45.
As shown in FIGS. 45 through 48, this conventional photoelectric conversion device includes a photodiode 1 for generating and accumulating an electric charge (hereinafter referred to simply as a charge) in response to incident light. A junction field-effect transistor (JFET) 2 receives (at the gate region thereof) the charge from the photodiode 1 and amplifies and outputs the charge. A transfer gate 3 transfers the charge generated and accumulated in the photodiode 1 to the gate region of the JFET 2. A reset drain 4 controls the electric potential of the gate region of the JFET 2. A reset gate 5 controls the electrical connection between the gate region of the JFET 2 and the reset drain 4.
The photodiode 1, the JFET 2, and the reset drain 4 are formed in an N-type well region 11 formed on a P-type semiconductor substrate 10. The transfer gate 3 and the reset gate 5 are formed above the N-type well region 11, separated from the N-type well region 11 by an insulating film.
As shown in FIGS. 47 and 48, the photodiode 1 has a P-type charge-accumulation region 12 formed in the N-type well region 11 on the P-type semiconductor substrate 10, and a high-density N-type semiconductor layer 13 formed on the P-type charge-accumulation region 12 and near the top surface of the semiconductor. Thus a buried photodiode having an NPNP vertical overflow drain structure (or more precisely, an NPN buried photodiode, and a PNP overflow drain) is formed, as considered in the direction from the semiconductor surface toward the semiconductor substrate 10.
The JFET 2 has a P-type gate region 15 formed in the N-type well region 11. The JFET 2 also has an N-type source region 14 and an N-type channel region 17, both of which are formed in the P-type gate region 15. The JFET 2 further has an N-type drain region 16, formed opposite the source region 14 with the channel region 17 between, as shown in FIGS. 46 and 47.
As shown in FIG. 45, the N-type drain region 16 of the JFET 2 extends around the entire photoelectric conversion device, and it thus becomes the boundary region between any two adjacent photoelectric conversion devices. The N-type drain region 16 is continuous with the high-density N-type semiconductor layer 13 lying near the top surface of the photodiode 1 and the N-type well region 11, as shown in FIGS. 46 through 48. Accordingly, the N-type regions 11 and 13, in the PN junction which constitutes the photodiode 1, are electrically connected to the N-type drain region 16 of the JFET 2.
The P-type gate region 15 of the JFET 2 sandwiches the N-type channel region 17 from above and below. This structure can reduce the substrate-bias effect, and can increase the gain of the source follower action, while reducing variation in the gain.
The transfer gate 3 consists of a gate electrode positioned above the boundary between the P-type charge-accumulation region 12 and the P-type gate region 15 of the JFET 2, and separated from the boundary by an insulating film, as shown in FIG. 47. The transfer gate 3 transfers the charge accumulated in the P-type charge-accumulation region 12 of the photodiode 1 to the P-type gate region 15 of the JFET 2.
Thus, the P-type charge-accumulation region 12, the transfer gate 3, and the P-type gate 15 of the JFET 2 together constitute a P-channel MOS transistor.
The reset drain 4 has a P-type charge-drain region 18 formed in the N-type well region 11, as shown in FIGS. 46 and 48. The reset drain 4 controls the electric potential of the P-type gate region 15 of the JFET 2 via the reset gate 5.
The reset gate 5 consists of a gate electrode positioned above the boundary between the P-type gate region 15 of the JFET 2 and the P-type charge-drain region 18. The gate electrode is separated from the boundary region by an insulating film, as shown in FIG. 46. The reset gate 5 controls the electrical connection between the P-type gate region 15 of the JFET 2 and the P-type charge-drain region 18 of the reset drain 4.
The P-type gate 15 of the JFET 2, the reset gate 5, and the P-type charge-drain region 18 of the reset drain 4 together constitute a P-channel MOS transistor.
The conventional photoelectric conversion device also has a transfer gate interconnection 20, a reset gate interconnection 21, a relay interconnection 23, a reset drain interconnection 24, a vertical signal line 22, and a drain interconnection 25, as shown in the figures.
FIGS. 49 through 52 illustrate a portion of a conventional photoelectric conversion apparatus that uses the photoelectric conversion device(s) of FIGS. 45-48 as pixels arranged in a matrix. FIG. 49 is a plan view; FIG. 50 is a cross-sectional view taken along the X1-X2 line shown in FIG. 49; FIG. 51 is a cross-sectional view taken along the Y1-Y2 line shown in FIG. 49; and FIG. 52 is a cross-sectional view taken along the Y3-Y4 line shown in FIG. 49.
In this conventional photoelectric conversion apparatus, the N-type source regions 14 of the JFETs 2 in each column of the pixel matrix are connected in common to the associated vertical signal line 22 in the vertical scanning direction.
The N-type drain regions 16 of the JFETs 2 of each pixel are continuous around the pixels and from pixel to pixel, extending like a lattice surrounding the pixels, as shown in FIG. 49. The N-type drain regions 16 of each column are each connected in common, in the vertical scanning direction, to the associated drain interconnection 25 via a contact hole 32 (FIG. 49) formed in the interlayer insulating film 33 (FIG. 50). The drain interconnections 25 are connected in common to another interconnection (not shown) at the top end and at the bottom end of the pixel matrix.
The drain interconnections 25 are formed for the purpose of supporting or reinforcing the diffusion layer of the N-type drain regions 16 with metal interconnections in order to reduce (or shunt) the resistance, and they are required for a photoelectric conversion apparatus having a sufficiently large number of pixels (for example, 500 to 1000 pixels in both the horizontal and vertical directions). If the number of pixels is relatively small, the drain interconnections 25 may be omitted.
As shown in FIG. 49, the transfer gates 3 in each row are connected in common, in the horizontal scanning direction, to the associated transfer gate interconnection 20. The reset gates 5 in each row are similarly connected in common, also in the horizontal scanning direction, to the associated reset gate interconnection 21.
As shown in FIGS. 50 and 52, the charge-drain regions 18 of the reset drains 4 in each row are connected in common, in the horizontal scanning direction, to the associated reset drain interconnection 24. This connection is made for each charge-drain region 18 via a contact hole 30 formed in the interlayer insulating film 33, a relay interconnection 23, and a relay interconnection hole 31. The reset drain interconnection 24 also functions as a light-blocking layer for blocking light incident to areas other than the photodiode 1 (FIG. 49).
FIG. 53 is a circuit diagram of the conventional photoelectric conversion apparatus. An individual photoelectric conversion device includes the circuit elements within the broken line in FIG. 53. Each photoelectric conversion device, which functions as a pixel, comprises a photodiode 1, a JFET 2, a transfer gate 3, a reset drain 4, and a reset gate 5. The N-type region of the photodiode 1 is connected to the drain region D of the JFET 2, as shown in FIGS. 45 through 48. The P-type charge-accumulation region 12 of the photodiode 1, the transfer gate 3, and the gate region 15 of the JFET 2 together constitute a P-channel MOS transistor. The gate region 15 of the JFET 2, the reset gate 5, and the reset drain 4 together likewise constitute a P-channel MOS transistor.
Although not shown in FIG. 53, the photodiode 1, as explained above, has a vertical overflow drain structure that functions to allow any excess charge to overflow to the P-type semiconductor substrate.
The source regions S of the JFETs 2 in each column of the pixel matrix are connected in common to one of the vertical signal lines 22a-22d.
The drain regions D of the JFETs 2 of all the pixels are connected in common to the drain voltage source VD by the N-type diffusion layer, formed in a lattice as shown in FIGS. 49 through 52, which becomes the N-type drain region 16, and by the drain interconnections 25 (FIGS. 49 and 50).
The transfer gates 3 in each row are each connected in common, in the horizontal scanning direction, to a respective one of the transfer gate interconnections 20a-20c which are connected to a vertical scanning circuit 7. The vertical scanning circuit 7 supplies driving pulses .phi.TG1-.phi.TG3 respectively to the transfer gate interconnections 20a-20c, each of the driving pulses .phi.TG1-.phi.TG3 thus activating all of the transfer gates 3 in a respective row.
The reset gates 5 in each row are connected in common, in the horizontal scanning direction, to a respective one of the reset gate interconnections 21a-21c, which in turn are connected in common at the left and right ends of the pixel matrix. (Only the left end is shown in FIG. 53.) Accordingly, all the reset gates are activated at the same time by a driving pulse .phi.RG.
The reset drains 4 in each row are connected in common, in the horizontal scanning direction, to a respective one of the reset drain interconnections 24a-24c, which are connected to the vertical scanning circuit 7. The vertical scanning circuit 7 supplies driving pulses .phi.RD1-.phi.RD3, respectively, to the reset drain interconnections 24a-24c, each pulse activating the reset drains 4 in a respective row.
The sources S of the JFETs 2 in each column are connected in common to a respective one of the vertical signal lines 22a-22d. Each of the vertical signal lines 22a-22d is connected at one end to a respective one of the photosignal output storage capacitors CS1-CS4 via a respective one of the associated photosignal output transfer MOS transistors TS1-TS4. The capacitors CS1-CS4 are connected, along with the outputs of the output transfer MOS transistors TS1-TS4, to a horizontal signal line (i.e., the signal output line) 27a, via a respective one of the horizontal selection MOS transistors THS1-THS4.
Each of the vertical signal lines 22a-22d is also connected, at the same one end, to a respective one of the dark-output storage capacitors CD1-CD4, via a respective one of the dark-output transfer MOS transistors TD1-TD4. The dark-output storage capacitors CD1-CD4 and the dark-output transfer MOS transistors TD1-TD4 are further connected to a horizontal signal line (i.e., the dark output line) 27b, via a respective one of the horizontal selection MOS transistors THD1-THD4.
The MOS transistors TS1-TS4 and the MOS transistors TD1-TD4 are activated respectively by driving pulses .phi.TS and .phi.TD. A horizontal scanning circuit 8 supplies driving pulses .phi.H1-.phi.H4, which activate the MOS transistors THS1-THS4, respectively, and, in parallel, the MOS transistors THD1-THD4, respectively.
The horizontal signal lines 27a and 27b are connected respectively to the output buffer amplifiers 28a and 28b, and to the horizontal signal line reset MOS transistors TRHS and TRHD. The reset MOS transistors TRHS and TRHD are activated by a driving pulse .phi.RH. The horizontal signal lines 27a and 27b have parasitic capacitances CHS and CHD, respectively.
The vertical signal lines 22a-22d are also connected respectively to the vertical signal line reset MOS transistors TRV1-TRV4, and to the constant-current sources 26a-26d that are in turn connected to a low-potential voltage source VCS. The reset MOS transistors TRV1-TRV4 for the vertical signal lines 22a-22d are activated by a driving pulse .phi.RV.
FIG. 54 is a timing chart showing the operation of the conventional photoelectric conversion apparatus shown in FIG. 53. Since the transfer gate 3 and the reset gate 5 of each photoelectric conversion device (each unit pixel of the apparatus) are of the P-channel-type as shown in FIGS. 45 through 48, the polarities of the driving pulses .phi.TG1-.phi.TG3 and the driving pulse .phi.RG are opposite to the polarities of the rest of the pulses. Accordingly, when the pulses .phi.TG1-.phi.TG3 and .phi.RG are at a low level, the associated transfer gates 3 and the reset gates 5 are in the connected state (ON state); when these pulses are at a high level, the transfer gates 3 and the reset gates 5 are in the disconnected state (OFF state).
In FIG. 54, the periods t11 through t15 show the readout operation for the first-row pixels. The periods t21 through t25 are for the second-row pixels. The periods t31 through t35 are for the third-row pixels.
In the interval t11, a current (i.e., the first) row is selected and the JFETs 2 of the first row are initialized. In the interval t12, source-follower action occurs, based on charge present at the gates of the first-row JFETS 2 after initialization. In the interval t13, signal charges are transferred from the first-row photodiodes 1 to the associated JFETs 2. In interval t14, source-follower action occurs based on the charges present at the gates of the first-row JFETS 2 after the signal charges are transferred to the first-row JFETs 2. These four operations (in t11 through t14) are performed within the period of a horizontal retrace line. In interval t15, a video signal is output.
More specifically, at the beginning of t11, the driving pulse .phi.RD1 is raised to a high level, while the driving pulses .phi.RD2 and .phi.RD3 are kept at a low level, whereby a high-level voltage is applied to the reset drains 4 of the first-row pixels, and a low level voltage is applied to the reset drains 4 of the second-row and third-row pixels. At this time (t11), driving pulse .phi.RG is and has been low, and the reset gates 5 of all the pixels are and have been in the ON state (i.e., connected state). Accordingly, the high-level voltage is transferred to the gate regions of the JFETs 2 of the first-row pixels, while the low-level voltage is transferred to the gate regions of the JFETs 2 of the second-row and third-row pixels, via the reset gates 5. As a result, the first-row JFETs 2 are turned on (that is, selected), and the JFETs 2 of the second and later rows are turned off (that is, not selected).
At the end of t11, the driving pulse .phi.RG is raised to the high level, and the reset gates 5 of all the pixels are shut off, whereby the gate regions of the JFETs 2 of each row are placed into a floating state, while maintaining their respective ON (i.e., selected) or OFF (i.e., non-selected) states. In other words, the gate regions of the JFETs 2 of the selected row (i.e., the first row in this case) are reset to the high-level initial state, and the gate regions of the JFETs 2 of the non-selected rows are reset to the low-level initial state.
At the beginning of t12, the driving pulse .phi.RV is changed to the low level, and the reset transistors TRV1-TRV4 are turned off, which causes the first-row JFETs 2 to perform a source-follower action. In the interval t12, the driving pulse .phi.TD is kept at the high level, and the dark-output transfer MOS transistors TD1-TD4 are in the ON state (i.e., the connected state). Consequently, the initialized voltages (i.e., dark-output voltages), which represent the electric potentials of the gate regions of the JFETs 2 immediately after the initialization, are supplied to the dark-output storage capacitors CD1-CD4.
At the beginning of t13, the driving pulse .phi.TG1 is changed to the low level, while the driving pulses .phi.TG2 and TG3 are kept at the high level, whereby the transfer gates 3 of the first-row pixels are turned on. Signal charges generated and accumulated in the photodiodes 1 of the first-row pixels are thus transferred to the gate regions of the first-row JFETs 2. The voltage of the gate region of each first-row JFET 2 changes, immediately after the charge transfer, by an amount represented by the fraction: (transferred signal charge)/(gate capacitance). In this example, the voltage increases.
At the end of t13, the driving pulse .phi.TGL is raised to the high level, and the transfer gates 5 are turned off, whereby the first-row photodiodes 1 start generating and accumulating new signal charges by photoelectric conversion. In FIG. 54, tLI indicates the charge-accumulation time of the photodiode.
At the beginning of t14, as at t12, the driving pulse .phi.RV is changed to the low level, and the reset transistors TRV1-TRV4 are turned off, which causes the first-row JFETs 2 to perform source-follower action. In the interval t14, the driving pulse .phi.TS is kept at the high level, and the photosignal output transfer MOS transistors TS1-TS4 are in the ON state (i.e., the connected state). Consequently, output voltages, which represent the electric potentials of the gate regions of the JFETs 2 after the receipt of the transferred charges, are supplied to the photosignal output storage capacitors CS1-CS4.
The constant-current sources 26a-26d apply a load to the JFETs 2 in the intervals t12 and t14 in order to control the activation points and the operation speeds of the JFETs 2.
The charge-amplification rate of the source-follower action is defined by the ratio of the photosignal output storage capacitance CS (of the respective output storage capacitor) to the gate capacitance Cg of each JFET 2 (CS/Cg), and it is possible to obtain an amplification rate as high as several hundred to one thousand or more.
Because the source-follower action of the JFETs of this conventional example are performed row-by-row within a horizontal-retrace-line period, the amplification time can be increased as compared with a photoelectric conversion apparatus in which the charge is amplified pixel-by-pixel in synchrony with the horizontal scanning based on, for example, the driving pulses .phi.H1-.phi.H4. Consequently, the capacitance of the photosignal output storage capacitors CS1-CS4 and the dark-output storage capacitors CD1-CD4 can be made larger, which can narrow the operational bandwidth of the source-follower action by a factor of 1/10 to 1/100. Thus, the noise due to amplification can be substantially reduced.
At t15, the horizontal scanning circuit 8 outputs driving pulses .phi.H1-.phi.H4 successively, which cause the charges accumulated in the photosignal output storage capacitors CS1-CS4, and in the dark-output storage capacitors CD1-CD4, to be transferred to the horizontal signal line 27a (the photosignal output line), and to the horizontal signal line 27b (the dark-output line), respectively. The potential of these lines 27a and 27b are output, via the output buffer amplifiers 28a and 28b, from output terminals VOS and VOD as video signals. The driving pulse .phi.RH is triggered successively in order to reset the horizontal signal lines 27a and 27b.
The video signals obtained from the output terminals VOS and VOD are subjected to a subtraction operation by an external arithmetic unit (not shown) in order to remove the dark component. In other words, the video signal output from the output terminal VOD, which contains only a dark component, is subtracted from the video signal output from the output terminal VOS, which contains a photosignal component and a dark component. As a result of this substraction (VOS-VOD), a video signal representing only the photosignal component can be extracted.
The dark component contained in both VOS and VOD includes a fixed-pattern noise component due to variation of the threshold voltage of each JFET 2, a reset noise component generated in the channel region under the reset gate 5 when the gate region of each JFET 2 is reset (or initialized) via the reset drain 4 and the reset gate 5, and a 1/f noise component generated during the source-follower action by the JFET 2 and the constant-current sources 26a-26d.
By subtracting VOD from VOS, the noise components listed above are removed, and a video signal containing only a photosignal component can be obtained, and the S/N ratio is improved.
The readout operation for the first pixel row during the periods t11 through t15 is repeated for the second and third pixel rows in the periods t21 through t25 and t31 through t35, respectively.
The photoelectric conversion apparatus shown in FIGS. 49 through 53 employs a plurality of conventional photoelectric conversion devices (shown in FIGS. 45 through 48) arranged in a matrix. Each device has a vertical overflow drain structure, and employs a buried photodiode. Therefore, dark current, afterimage, reset noise, blooming, and smear are reduced. In addition, the narrow-bandwidth source-follower action of the JFET 2, using the photosignal output storage capacitance and the dark-output storage capacitance as a load, can increase the charge-amplification rate, while reducing the noise during the amplification process. The subtraction of VOD from VOS can reduce the fixed-pattern noise component due to the variation of the threshold voltage of each JFET 2, the reset noise component generated when the gate region of each JFET 2 is reset (or initialized), and the 1/f noise component generated during the source-follower action.
The conventional photoelectric conversion apparatus shown in FIGS. 49 through 53 thus has the advantage that a highly sensitive video signal can be obtained with a reduced noise component (i.e., an improved S/N ratio). However, this conventional photoelectric conversion apparatus, using the photoelectric conversion devices shown in FIGS. 45-48 arranged in a matrix, has the disadvantage that the production yield is low.
In the conventional photoelectric conversion apparatus shown in FIGS. 49-52, drain interconnections 25 are formed for the purpose of preventing the drain voltages applied to the JFETs 2 from varying excessively among the pixels. If drain interconnections are not used, and a drain voltage is applied to the JFET 2 of each pixel only from the periphery of the pixel matrix via the diffusion layer that becomes the drain region 16, a potential drop occurs due to significant parasitic resistance, causing the drain voltage applied to the JFETs 2 to vary excessively among the pixels.
The drain interconnections 25 and the vertical signal lines 22 are formed in the same manufacturing process step. First, a metal layer, which is the material of the interconnection, is deposited. Then, vertical signal lines 22 and drain interconnections 25 are formed by a photolithography/etching process including a pattern-transfer step and an etching step. The two types of lines are formed in the vertical scanning direction (that is, the vertical direction in FIG. 49), parallel to each other, with a relatively narrow gap between any two adjacent lines. Accordingly, a particle whose size is equal to or greater than the gap between the lines may adhere to adjacent lines during the photolithography/etching process. If such a particle adheres, two adjacent lines are connected to each other, and a short-circuit mode malfunction occurs, which causes the production yield to drop.
Furthermore, the charge-drain region 18 of the reset drain 4 is connected to the reset drain interconnection 24 via a contact hole 30, a relay interconnection 23, and a relay connection hole 31, all of which are formed in the interlayer insulating film 33. This structure is made by repeating photolithography/etching steps and the steps of depositing an insulating film and a metal layer. During these steps, a particle whose size is greater than the diameter of the contact hole 30 or the relay connection hole 31 may adhere to the sides of the contact hole 30 or the relay interconnection hole 31. In this case, the electrical connection between the reset drain 4 and the reset drain interconnection 24 is damaged by the attached particle, which causes an open-mode malfunction.
An open-mode malfunction prevents the JFET 2 from being properly controlled. In such a malfunction, the JFET 2, which is normally ON, keeps on supplying pseudo signals from its source region to the vertical signal line 22. In other words, if a faulty electrical connection to the reset drain 4 occurs even at a single point, not only the corresponding pixel, but also the entire column of pixels including the corresponding pixel in which the faulty connection occurred, generates defective video signals, causing a defective vertical line in the resultant image. This open-mode defect also results in decreased production yield.
These two different types of defects become significant as the number of photoelectric conversion devices arranged in the matrix increases. Especially, if 500 to 1000 or more pixels are aligned in both the horizontal and vertical directions in a photoelectric conversion apparatus, these defects cause the production yield to drop significantly.
Another example of a known solid-state image sensor is disclosed in Shinohara et al., "Development of a Bipolar-type Area Sensor BASIS", published in VIDEO INFORMATION INDUSTRIAL, the Video Information Editorial Dept., Sangyo Kaihatsu Kikou Kabushiki Kaisya, May 1989, pp. 41-46. This bipolar solid-state image sensor will be briefly explained with reference to FIGS. 55 through 59. FIG. 55 is a schematic plan view of this solid-state image sensor. FIG. 56 is a cross-sectional view taken along the X11-X12 line shown in FIG. 55. FIG. 57 is a cross-sectional view taken along the X13-X14 line shown in FIG. 55. FIG. 58 is a cross-sectional view taken along the Y11-Y12 line shown in FIG. 55. FIG. 59 is a circuit diagram showing the basic structures of the pixel and the readout circuit of the solid-state image sensor. In FIG. 58, only a single pixel is illustrated.
The conventional bipolar solid-state image sensor shown in FIGS. 55 through 58 has a base consisting of a high-density (high dopant density) N-type semiconductor substrate 301 and a low-density epitaxial layer (N-type semiconductor layer 302). Multiple pixels are arranged in a two-dimensional matrix, together with associated readout circuits, in and on the base.
As shown in FIG. 59, each pixel comprises an npn-type bipolar transistor Tr, a PMOSFET 303, and a capacitor Cox formed on the bipolar transistor Tr.
Each readout circuit includes a capacitor Ct for temporarily storing a voltage output from the emitter of the bipolar transistor Tr. A transfer MOSFET 304, controlled by a driving pulse .phi.T, connects the capacitor Ct to a vertical output line VL. A reset MOSFET 305 resets the vertical output line VL.
The operation of the pixel consists of a charge-accumulation step, a readout step, and a reset step.
At the end of the reset step, when a reverse bias has been applied between the base and the emitter of the bipolar transistor Tr, charge-accumulation starts. As holes generated in response to incident light are accumulated in the base region of the bipolar transistor Tr, the base voltage VB rises, and the depletion layer between the base and the collector of the bipolar transistor Tr decreases.
Next, the reset MOSFET 305 is turned off, whereby the emitter of the bipolar transistor Tr is placed in a floating state. The driving pulse .phi.R of the horizontal driving line HL is then raised to the positive level, thus raising the base voltage in the positive direction by capacitive coupling via the capacitor Cox. Thus a forward bias is applied between the base and the emitter of the bipolar transistor Tr. At this point in time, the readout action starts.
The emitter voltage VE, which has a capacitive load, approaches the base voltage until the potential difference reaches a certain value by the end of readout action. The change of the base voltage during the charge-accumulation step is thus reflected at the emitter terminal of the bipolar transistor Tr.
The reset step includes a pair of reset actions. The first reset action comprises turning on the PMOSFET 303 by setting the driving pulse .phi.R low. This grounds the base of the bipolar transistor Tr. The second reset action comprises setting the driving pulse .phi.VC to positive, and grounding the emitter of the bipolar transistor Tr while raising the driving pulse .phi.R to the positive. As a result, the base of the bipolar transistor Tr is raised to positive, a forward bias is applied between the base and the emitter, and the base potential drops due to the recombination of electrons and holes. When the voltage .phi.R returns to the ground level, the reset action terminates, and the next charge-accumulation starts.
FIGS. 55 through 58 illustrate the pixel structure of the conventional solid-state image sensor. The bipolar transistor Tr comprises a P-type diffusion region 306, which functions as the base, a high-density N-type diffusion region 307, which functions as the emitter, and an N-type semiconductor substrate 301 and an N-type semiconductor layer 302, which constitute a collector. A metal layer 308 is formed as a collector electrode on the bottom surface of the substrate 301. Accordingly, the bipolar transistor Tr is a device that is activated by a voltage applied from the metal layer 308, via the high-density N-type semiconductor substrate 301 and the low-density N-type semiconductor layer 302, in that order.
The pixel structure also includes a polysilicon relay interconnection 309 from high-density N-type diffusion region 307 to an Al (aluminum) interconnection 310 (which interconnection corresponds to the vertical output line VL). A high-density N-type diffusion region 311, positioned between any two adjacent pixels, functions as a pixel-separating region. A polysilicon interconnection 312 (corresponding to the horizontal driving line HL) drives the P-type diffusion region 306 (the base of the bipolar transistor Tr of each pixel) by capacitive coupling across an oxide-film capacitor Cox.
The polysilicon interconnection 312 also functions as the gate electrode of the PMOSFET 303. The PMOSPET 303 is positioned in the pixel boundary, and the polysilicon interconnection 312 becomes the gate of the PMOSFET 303.
The Al interconnection 310 is placed above the polysilicon interconnection 312 in order to block incident light. If the gate (i.e., the polysilicon interconnection 312) of the PMOSFET 303 is turned on, the bases (i.e., the P-type diffusion layers 306) of adjacent bipolar transistors Tr are electrically connected. If the gate of the PMOSFET 303 is turned off, the N-type diffusion region 311 functions as a pixel-separating region. A portion of the polysilicon interconnection 312 which overlaps the P-type diffusion region 306 (i.e., the base of the bipolar transistor Tr) forms part of the capacitor Cox. Isolating regions are formed by an SiO2 film 313 and a LOCOS 314.
As has been mentioned earlier, in the conventional bipolar solid-state image sensor, the bipolar transistor Tr is activated by a voltage applied via the high-density N-type semiconductor substrate 301 and the low-density semiconductor layer 302, in this order.
Only N-type diffusion regions 311 are formed between adjacent pixels in order to separate these pixels. Although the N-type diffusion region 311 can reduce the crosstalk between two adjacent pixels, such reduction requires the use of the low-density N-type semiconductor layer 302. The low-density N-type semiconductor layer 302 has a high resistance which negatively affects activation of the transistor Tr by a voltage applied via the high-density N-type semiconductor substrate 301 and the low-density semiconductor layer 302.
Further, in the conventional bipolar solid-state image sensor, in order to spread the detection sensitivity toward the long wavelength side, the impurity concentration of the N-type semiconductor layer 302 must be decreased, and the thickness of the depletion layer between the P-type base (i.e., P-type diffusion layer 306) and the N-type collector (i.e., N-type semiconductor layer 302) must be increased. However, because of the reduced impurity concentration of the N-type semiconductor layer 302, the resistance of this N-type layer becomes high, and the voltage supplied from the N-type semiconductor substrate 301 is not sufficiently transferred through the N-type semiconductor layer 302. This degrades the performance of the bipolar transistor Tr and increases the variation in the production process, decreasing production yield. As a whole, the quality of the solid-state image sensor deteriorates.
This situation applies not only to the bipolar solid-state image sensor shown in FIGS. 55 through 59, but also to any solid-state image sensor that has a base consisting of a first conductive-type higher-density semiconductor substrate and a first conductive-type lower-density semiconductor layer formed on the substrate, with a pixel matrix in and on the base, with each pixel including a device to which a voltage is applied via the semiconductor substrate and the semiconductor layer, in that order.
In a solid-state image sensor, the impurity concentration of the first conductive-type semiconductor layer may need to be decreased for various reasons, in addition to increasing the sensitivity to long wavelengths and decreasing cross-talk between pixels.